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PIC16LC74B-16/PTL16
8-Bit CMOS Microcontrollers with A/D Converter
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
44 43 42 41 40 39 38 37 36 35 34
PIC16LC74B-16/PTL16 Microcontroller Core Features:
* High-performance RISC CPU * Specially tested - 16MHz @ 3V * Only 35 single word instructions to learn * All single cycle instructions except for program branches which are two cycle * Operating speed: DC - 16 MHz clock input DC - 250 ns instruction cycle * 4K x 14 words of Program Memory, 192 x 8 bytes of Data Memory (RAM) * Interrupt capability * Eight level deep hardware stack * Direct, indirect and relative addressing modes * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Selectable oscillator options * Low-power, high-speed CMOS EPROM technology * Wide operating voltage range: 2.5V to 5.5V * High Sink/Source Current 25/25 mA * Commercial, Industrial and Automotive temperature ranges * Low-power consumption: - < 5 mA @ 5V, 4 MHz - 23 A typical @ 3V, 32 kHz - < 3 A typical standby current
Pin Diagram:
TQFP
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler can be incremented during sleep via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Capture, Compare, PWM module(s) - Capture is 16 bit, max. resolution is 15.6 ns - Compare is 16 bit, max. resolution is 250 ns - PWM max. resolution is 10 bit * 8-bit multichannel analog-to-digital converter * Synchronous Serial Port (SSP) with SPITM and I2CTM * Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) * Parallel Slave Port (PSP), 8-bits wide, with external RD, WR and CS controls * Brown-out detection circuitry for Brown-out Reset (BOR) Pin Diagrams
(c) 1999 Microchip Technology Inc.
Preliminary
NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 PIC16LC74B-16/PTL16 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/SS/AN4 RA4/T0CKI
DS30026A-page 1
PIC16LC74B-16/PTL16
Table of Contents
1.0 General Description ................................................................................................................................................. 3 2.0 Electrical Characteristics.......................................................................................................................................... 5 3.0 DC and AC Characteristics Graphs and Tables..................................................................................................... 27 4.0 Packaging Information ........................................................................................................................................... 29 Index ............................................................................................................................................................................. 33 On-Line Support ............................................................................................................................................................ 35 Reader Response ......................................................................................................................................................... 36 Product Identification System........................................................................................................................................ 37
To Our Valued Customers
Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: * Fill out and mail in the reader response form in the back of this data sheet. * E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.
DS30026A-page 2
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
1.0 GENERAL DESCRIPTION
This data sheet covers the PIC16LC74B-16/PTL16 device. The functional characteristics of this device are identical to the PIC16LC74B. For electrical specifications, see the electrical specifications contained within this document. For all other information about this device, see the PIC16C63A/65B/73B/74B data sheet (DS30605).
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 3
PIC16LC74B-16/PTL16
NOTES:
DS30026A-page 4
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
2.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings () Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined)..................................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) ............................................................200 mA Maximum current sunk by PORTC and PORTD (combined) ................................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) ...........................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device, at those or any other conditions above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 5
PIC16LC74B-16/PTL16
FIGURE 2-1: PIC16LC74B-16/PTL16 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V Voltage (VDD) 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V
4 MHz
8 MHz Frequency (MHz)
16 MHz
Fmax = (24 MHz/V)(VDD.APP.MIN - 2.5V) + 4 MHz Note: VDD.APP.MIN is the minimum VDD of the PICmicro(R) device in the application. Fmax is no greater than 16 MHz.
DS30026A-page 6
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
2.1 DC Characteristics: PIC16LC74B-16/PTL-04 (Commercial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial Min Typ Max Units Conditions 2.5 VBOR* TBD VSS 5.5 5.5 V V V V RC, LP, XT, HS osc modes (DC - 4 MHz) BOR enabled (Note 7) DC CHARACTERISTICS Param No. D001 D002* D003 Sym VDD VDR VPOR Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset voltage trip point Supply Current (Note 2, 5)
D004* SVDD D004A* D005 D010 VBOR IDD
0.05 TBD 3.65 -
2.0 3.0 22.5
4.35 3.8 6.0 48
V/mS PWRT enabled (PWRTE bit clear) V/mS PWRT disabled (PWRTE bit set) V mA mA A BODEN bit set XT, RC osc modes FOSC = 4 MHz, VDD = 3.0V (Note 4) HS oscillator mode Fosc = 16MHz, VDD = 3.0V LP osc mode FOSC = 32 kHz, VDD = 3.0V, WDT disabled VDD = 3.0V, WDT disabled, 0C to +70C
D010A D021 IPD
-
D022* D022A* * Note 1: 2:
3: 4: 5: 6: 7:
Power-down Current 0.9 5 A (Note 3, 5) Module Differential Current (Note 6) IWDT Watchdog Timer 6.0 20 A WDTE bit set, VDD = 4.0V IBOR Brown-out Reset 350 425 A BODEN bit set, VDD = 5.0V These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD. MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 7
PIC16LC74B-16/PTL16
2.2 DC Characteristics: PIC16LC74B-16/PTL-04 (Commercial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 2.1 Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. Sym Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP modes) Input High Voltage I/O ports with TTL buffer
VIL D030 D030A D031 D032 D033
VSS VSS VSS Vss Vss
-
0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD
V V V V V
For entire VDD range 4.5V VDD 5.5V
Note1
VIH D040 D040A
2.0 0.25VDD + 0.8V
-
VDD VDD
V V
4.5V VDD 5.5V For entire VDD range
D041 D042 D042A D043
D060 D061 D063 D070 D080
IIL
with Schmitt Trigger buffer 0.8VDD MCLR 0.8VDD OSC1 (XT, HS and LP modes) 0.7VDD OSC1 (in RC mode) 0.9VDD Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1 50 -
-
VDD VDD VDD VDD
V V V V
For entire VDD range Note1
250 -
1 5 5 400 0.6 0.6 0.6 0.6
A A A A V V V V
IPURB VOL
PORTB weak pull-up current Output Low Voltage I/O ports
Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc modes VDD = 5V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C
D083
OSC2/CLKOUT (RC osc mode)
-
D090 *
VOH
Output High Voltage I/O ports (Note 3)
VDD-0.7
-
-
V
These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the device be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
DS30026A-page 8
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
2.2 DC Characteristics: PIC16LC74B-16/PTL-04 (Commercial) (Cont.'d)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 2.1 Min Typ Max Units Conditions VDD-0.7 D092 OSC2/CLKOUT (RC osc mode) VDD-0.7 VDD-0.7 D150* Open-Drain High Voltage Capacitive Loading Specs on Output Pins COSC2 OSC2 pin VOD 8.5 V V V V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin
DC CHARACTERISTICS Param No. Sym Characteristic
D100
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101 D102
CIO
All I/O pins and OSC2 (in RC mode)
-
-
50
pF
400 pF Cb SCL, SDA in I2C mode These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the device be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. *
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 9
PIC16LC74B-16/PTL16
2.3
2.3.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free T Time 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only)
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid Hi-impedance High Low
TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition
SU STO
Setup STOP condition
DS30026A-page 10
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
2.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 2-1 apply to all timing specifications unless otherwise noted. Figure 2-2 specifies the load conditions for the timing specifications.
TABLE 2-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 2.1. LC parts operate for commercial/industrial temp's only.
AC CHARACTERISTICS
FIGURE 2-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 VDD/2 CL VSS Pin VSS CL RL = 464 CL = 50 pF 15 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports for OSC2 output Load condition 2
RL
Pin
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 11
PIC16LC74B-16/PTL16
2.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 2-3:
EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 2-2:
Param No. 1A Sym Fosc
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Min
(Note 2)
Typ
Max
(Note 3)
Units
Conditions
DC -- 4 MHz RC and XT osc modes DC -- 4 MHz HS osc mode (-04) DC -- 20 MHz HS osc mode (-20) DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz RC osc mode (Note 1) 0.1 -- 4 MHz XT osc mode 4 -- 20 MHz HS osc mode 5 -- 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 -- -- ns RC and XT osc modes (Note 3) 250 -- -- ns HS osc mode (-04) 50 -- -- ns HS osc mode (-20) 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns RC osc mode (Note 3) 250 -- 10,000 ns XT osc mode 250 -- 250 ns HS osc mode (-04) 50 -- 250 ns HS osc mode (-20) 5 -- -- s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 -- DC ns TCY = 4/FOSC 3* TosL, External Clock in (OSC1) High 100 -- -- ns XT oscillator TosH or Low Time 2.5 -- -- s LP oscillator 15 -- -- ns HS oscillator 4* TosR, External Clock in (OSC1) Rise -- -- 25 ns XT oscillator TosF or Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. 2: All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. 3: When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30026A-page 12
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-4:
OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 12 18 16 11
CLKOUT AND I/O TIMING
Q4 Q1 Q2 Q3
20, 21 Note: Refer to Figure 2.1 for load conditions.
TABLE 2-3:
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18A* 19* 20A* 21A* 22* 23* * Sym
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time Min -- -- -- -- -- Tosc + 200 0 -- 200 0 -- -- TCY TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- -- -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 150 -- -- 80 80 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR TioF Tinp Trbp
TosH2ckH OSC1 to CLKOUT
These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 13
PIC16LC74B-16/PTL16
FIGURE 2-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins Note: Refer to Figure 2-2 for load conditions. 32 30
31
34
FIGURE 2-6:
BROWN-OUT RESET TIMING
BVDD VDD
35
TABLE 2-4:
Parameter No. 30 31* 32 33* 34 35 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Sym TmcL Twdt Tost Tpwrt TIOZ TBOR Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or WDT reset Brown-out Reset Pulse Width Min 2 7 -- 28 -- 100 Typ -- 18 1024 TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units Conditions
s
ms -- ms
VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
s s
VDD BVDD (D005)
These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30026A-page 14
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42 T1OSO/T1CKI
45
46
47 TMR0 or TMR1 Note: Refer to Figure 2-2 for load conditions.
48
TABLE 2-5:
Param No.
40* 41* 42*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic
T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler
Sym
Tt0H Tt0L Tt0P
Min
0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 25 50 0.5TCY + 20 25 50 Greater of: 50 OR TCY + 40 N 100 DC 2Tosc
Typ Max Units
-- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns
Conditions
Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4,..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8)
No Prescaler With Prescaler
45*
Tt1H
T1CKI High Time
46*
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1 Synchronous, Prescaler = 2,4,8 Asynchronous Synchronous, Prescaler = 1 Synchronous, Prescaler = 2,4,8
47*
Tt1P
Asynchronous T1CKI input period Synchronous
-- -- -- -- -- --
-- -- -- -- -- --
ns ns ns ns ns ns
48
Asynchronous Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment Ft1
-- -- --
-- 200 7Tosc
ns kHz --
*
These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 15
PIC16LC74B-16/PTL16
FIGURE 2-8: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx (Capture Mode)
50 52
51
CCPx (Compare or PWM Mode) 53 Note: Refer to Figure 2-2 for load conditions. 54
TABLE 2-6:
Param No. 50* Sym TccL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Characteristic CCP1 and CCP2 input low time No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 20 0.5TCY + 20 20 3TCY + 40 N -- -- Typ Max Units -- -- -- -- -- 25 25 -- -- -- -- -- 45 45 ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Conditions
51*
TccH CCP1 and CCP2 input high time TccP
52* 53* 54* *
CCP1 and CCP2 input period
TccR CCP1 and CCP2 output rise time TccF CCP1 and CCP2 output fall time
These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30026A-page 16
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-9:
RE2/CS
PARALLEL SLAVE PORT TIMING (PIC16LC74B-16/PTL16)
RE0/RD
RE1/WR
65 RD7:RD0 62 63 Note: Refer to Figure 2-2 for load conditions.
64
TABLE 2-7:
Parameter No. 62* 63* 64 65* *
PARALLEL SLAVE PORT REQUIREMENTS (PIC16LC74B-16/PTL16)
Sym Characteristic Data in valid before WR or CS (setup time) WR or CS to data-in invalid (hold time) RD and CS to data-out valid RD or CS to data-out invalid Min 20 35 -- 10 Typ -- -- -- -- Max -- -- 80 30 Units ns ns ns ns Conditions
TdtV2wrH TwrH2dtI TrdL2dtV TrdH2dtI
These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 17
PIC16LC74B-16/PTL16
FIGURE 2-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72 78 SCK (CKP = 1) 79 78 79
80 SDO MSb 75, 76 SDI MSb IN 74 73 Note: Refer to Figure 2-2 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSb
LSb IN
TABLE 2-8:
Param. No.
70 71 71A 72 72A 73 73A 74
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Characteristic Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 Typ Max Units -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns Conditions
Symbol
TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time Continuous (slave mode) Single Byte TscL TdiV2scH, TdiV2scL TB2B SCK input low time (slave mode) Continuous Single Byte Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge
Note 1 Note 1
Note 1
TscH2diL, 100 -- -- ns TscL2diL 75 TdoR SDO data output rise time -- 20 45 ns 76 TdoF SDO data output fall time -- 10 25 ns 78 TscR SCK output rise time (master mode) -- 20 45 ns 79 TscF SCK output fall time (master mode) -- 10 25 ns 80 TscH2doV, SDO data output valid after SCK edge -- -- 100 ns TscL2doV Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30026A-page 18
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSb 75, 76
BIT6 - - - - - -1
LSb
SDI
MSb IN 74
BIT6 - - - -1
LSb IN
Note: Refer to Figure 2.1 for load conditions.
TABLE 2-9:
Param. No.
71 71A 72 72A 73 73A 74
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Characteristic Continuous Single Byte SCK input low time Continuous (slave mode) Single Byte Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SCK input high time (slave mode) Min 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 Typ Max Units -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns Conditions
Symbol TscH TscL TdiV2scH, TdiV2scL TB2B
Note 1 Note 1
Note 1
TscH2diL, 100 -- -- ns TscL2diL 75 TdoR SDO data output rise time 20 45 ns 76 TdoF SDO data output fall time -- 10 25 ns 78 TscR SCK output rise time (master mode) 20 45 ns 79 TscF SCK output fall time (master mode) -- 10 25 ns 80 TscH2doV, SDO data output valid after SCK edge -- 100 ns TscL2doV 81 TdoV2scH, SDO data output setup to SCK edge TCY -- -- ns TdoV2scL Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 19
PIC16LC74B-16/PTL16
FIGURE 2-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72 83
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb IN 74 73 Note: Refer to Figure 2-2 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSb 77 LSb IN
TABLE 2-10:
Param. No.
70 71 71A 72 72A 73 73A 74
EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Characteristic Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 Typ Max Units -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns Conditions
Symbol
TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time Continuous (slave mode) Single Byte TscL TdiV2scH, TdiV2scL TB2B SCK input low time (slave mode) Continuous Single Byte Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge
Note 1 Note 1
Note 1
TscH2diL, 100 -- -- ns TscL2diL 75 TdoR SDO data output rise time 20 45 ns 76 TdoF SDO data output fall time -- 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 -- 50 ns 78 TscR SCK output rise time (master mode) 20 45 ns 79 TscF SCK output fall time (master mode) -- 10 25 ns 80 TscH2doV, SDO data output valid after SCK edge -- 100 ns TscL2doV 83 TscH2ssH, SS after SCK edge 1.5TCY + 40 -- -- ns TscL2ssH Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30026A-page 20
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82 SS
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
BIT6 - - - - - -1
LSb 77
SDI
MSb IN
BIT6 - - - -1
LSb IN
74 Note: Refer to Figure 2-2 for load conditions.
TABLE 2-11:
Param. No.
70 71 71A 72 72A 73A 74
EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Characteristic SS to SCK or SCK input Continuous Single Byte SCK input low time Continuous (slave mode) Single Byte Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SCK input high time (slave mode) Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 1.5TCY + 40 Typ Max Units -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns Conditions
Symbol TssL2scH, TssL2scL TscH TscL TB2B
Note 1 Note 1 Note 1
TscH2diL, 100 -- -- ns TscL2diL 75 TdoR SDO data output rise time 20 45 ns 76 TdoF SDO data output fall time -- 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 -- 50 ns 78 TscR SCK output rise time (master mode) -- 20 45 ns 79 TscF SCK output fall time (master mode) -- 10 25 ns 80 TscH2doV, SDO data output valid after SCK edge -- -- 100 ns TscL2doV 82 TssL2doV SDO data output valid after SS edge -- -- 100 ns 83 TscH2ssH, SS after SCK edge 1.5TCY + 40 -- -- ns TscL2ssH Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 21
PIC16LC74B-16/PTL16
FIGURE 2-14: I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition Note: Refer to Figure 2-2 for load conditions.
STOP Condition
TABLE 2-12:
Parameter No. 90* 91* 92* 93 *
I2C BUS START/STOP BITS REQUIREMENTS
Sym Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units Conditions Only relevant for repeated START condition After this period the first clock pulse is generated
TSU:STA THD:STA TSU:STO THD:STO
ns ns ns ns
These parameters are characterized but not tested.
DS30026A-page 22
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-15: I2C BUS DATA TIMING
103 SCL 100 101 90 91 SDA In 110 109 SDA Out Note: Refer to Figure 2-2 for load conditions. 109 106 107 92 102
TABLE 2-13:
Parameter No. 100*
I2C BUS DATA REQUIREMENTS
Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 100 kHz mode 400 kHz mode SSP Module 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1Cb -- 20 + 0.1Cb 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
Sym THIGH
101*
TLOW
Clock low time
s s
102*
TR
SDA and SCL rise time SDA and SCL fall time
ns ns ns ns s s s s ns s ns ns s s ns ns s s
Cb is specified to be from 10-400 pF Cb is specified to be from 10-400 pF Only relevant for repeated START condition After this period the first clock pulse is generated
103*
TF
90* 91* 106* 107* 92* 109* 110*
TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
START condition setup time START condition hold time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time
Note 2
Note 1 Time the bus must be free before a new transmission can start
Cb Bus capacitive loading -- 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 23
PIC16LC74B-16/PTL16
FIGURE 2-16: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin 120
121
121
122
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-14:
Param No. 120* 121* 122* * Sym
USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Characteristic SYNC XMIT (MASTER & SLAVE) Clock high to data out valid Clock out rise time and fall time (Master Mode) Data out rise time and fall time Min -- -- -- Typ -- -- -- Max 100 50 50 Units ns ns ns Conditions
TckH2dtV Tckrf Tdtrf
These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 2-17: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin
125
126 Note: Refer to Figure 2-2 for load conditions.
TABLE 2-15:
Parameter No. 125* 126* *
USART SYNCHRONOUS RECEIVE REQUIREMENTS
Sym TdtV2ckL TckL2dtl Characteristic SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) Data hold after CK (DT hold time) Min Typ Max Units Conditions
15 15
-- --
-- --
ns ns
These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30026A-page 24
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
TABLE 2-16:
Param Sym No. A01 A02 A03 A04 A05 A06 A10 A20 A25 A30 A40 NR Resolution
A/D CONVERTER CHARACTERISTICS: PIC16LC74B-16/PTL16-04 (COMMERCIAL)
Characteristic Min -- -- -- -- -- -- -- 2.5V VSS - 0.3 -- -- Typ -- -- -- -- -- -- guaranteed -- -- -- 90 Max 8 bits <1 <1 <1 <1 <1 -- VDD + 0.3 VREF + 0.3 10.0 -- Units bit LSb LSb LSb LSb LSb -- V V k A Average current consumption when A/D is on. (Note 1) During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD During A/D Conversion cycle Conditions VREF = VDD VREF = VDD VSS VAIN VREF VREF = VDD VSS VAIN VREF VREF = VDD VSS VAIN VREF VREF = VDD VSS VAIN VREF VREF = VDD VSS VAIN VREF VSS VAIN VREF
EABS Total Absolute error EIL EDL EFS Integral linearity error Differential linearity error Full scale error
EOFF Offset error -- VAIN ZAIN IAD Monotonicity (Note 3) Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD)
VREF Reference voltage
A50
IREF
VREF input current (Note 2)
10
--
1000
A
--
--
10
A
* These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 25
PIC16LC74B-16/PTL16
FIGURE 2-18: A/D CONVERSION TIMING
BSF ADCON0, GO 134 Q4 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLE SAMPLING STOPPED DONE 132 7 6 5 4 3 2 1 0 NEW_DATA 1 TCY (TOSC/2) (1) 131
OLD_DATA
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 2-17:
Param No. 130 131 Sym TAD TCNV
A/D CONVERSION REQUIREMENTS
Characteristic A/D clock period Conversion time (not including S/H time) (Note 1) Acquisition time Min 2.0 3.0 11 Note 2 5* Typ -- 6.0 -- 16 -- Max -- 9.0 11 -- -- Units s s TAD s s Conditions TOSC based, VREF full range A/D RC Mode VDD = 3.0V, Temp. = 100C, Rs = 10K The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
132
TACQ
134
TGO
Q4 to A/D clock start
--
TOSC/2
--
--
135
TSWC Switching from convert sample time
1.5
--
--
TAD
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See A/D section for minimum requirements.
DS30026A-page 26
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
3.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Graphs and Tables not available at this time.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 27
PIC16LC74B-16/PTL16
NOTES:
DS30026A-page 28
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
44-Lead TQFP MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE
Example
PIC16LC74B-16/PTL16/PT
9911HAT
Legend: MM...M XX...X AA BB C
D E Note:
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5" Line S = 6" Line H = 8" Line Mask revision number Assembly code of the plant or country of origin in which part was assembled
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 29
PIC16LC74B-16/PTL16
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E E1 #leads=n1 p
D1
D
B n
2 1
CH x 45 A
c
L A1 (F) Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10 MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10 A2
MIN
MAX
MIN
MAX
Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom
.039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5
.047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15
1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15
*Controlling Parameter Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076
DS30026A-page 30
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
APPENDIX A: REVISION HISTORY
Version A Date 6/99 Revision Description This is a new data sheet providing the electrical specifications for the 3V, 16 MHz device. For all other information, see the PIC16C63A/65B/73B/74B data sheet (DS30605).
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 31
PIC16LC74B-16/PTL16
NOTES:
DS30026A-page 32
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
INDEX A
A/D Converter Characteristics .......................................... 25 Timing Diagram .......................................................... 26 Absolute Maximum Ratings ................................................. 5
U
USART Synchronous Master Mode Timing Diagram, Synchronous Receive ............ 24 Timing Diagram, Synchronous Transmission .... 24
W
Watchdog Timer (WDT) Timing Diagram ......................................................... 14 WWW, On-Line Support ...................................................... 2
B
Brown-out Reset (BOR) Timing Diagram .......................................................... 14
C
Capture/Compare/PWM (CCP) Timing Diagram .......................................................... 16
D
DC Characteristics ............................................................... 8
E
Electrical Characteristics ...................................................... 5 Errata ................................................................................... 2
G
General Description ............................................................. 3
I
I2C (SSP Module) Timing Diagram, Data ................................................ 23 Timing Diagram, Start/Stop Bits ................................. 22
P
Packaging .......................................................................... 29 Parallel Slave Port (PSP) Timing Diagram .......................................................... 17 Power-on Reset (POR) Timing Diagram .......................................................... 14 Product Identification System ............................................ 37
R
Reset Timing Diagram .......................................................... 14 Revision History ................................................................. 31
T
Timer0 Timing Diagram .......................................................... 15 Timer1 Timing Diagram .......................................................... 15 Timing Diagrams and Specifications .................................. 12 A/D Conversion .......................................................... 26 Brown-out Reset (BOR) ............................................. 14 Capture/Compare/PWM (CCP) .................................. 16 CLKOUT and I/O ........................................................ 13 External Clock ............................................................ 12 I2C Bus Data .............................................................. 23 I2C Bus Start/Stop Bits ............................................... 22 Oscillator Start-up Timer (OST) ................................. 14 Parallel Slave Port (PSP) ........................................... 17 Power-up Timer (PWRT) ........................................... 14 Reset .......................................................................... 14 Timer0 and Timer1 ..................................................... 15 USART Synchronous Receive ( Master/Slave) ......... 24 USART SynchronousTransmission ( Master/Slave) .. 24 Watchdog Timer (WDT) ............................................. 14
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 33
PIC16LC74B-16/PTL16
DS30026A-page 34
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.
981103
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 35
PIC16LC74B-16/PTL16
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS30026A FAX: (______) _________ - _________
Device: PIC16LC74B-16/PTL16 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30026A-page 36
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16LC74B-16/PTL16
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -XX X /XX Package L16 Pattern Examples: a) PIC16LC74B-16/PTL16 = Commercial temp., TQFP package, 16 MHz, low voltage VDD limits,
QTP pattern #301.
Frequency Temperature Range Range
Device
PIC16LC7X(1), PIC16LC7XT(2);VDD range 2.5V to 5.5V
Frequency Range
04 16 20
= 4 MHz = 16 MHz = 20 MHz Note 1: 2: LC T = Low Voltage CMOS = in tape and reel - PLCC, QFP, TQFP packages only.
Temperature Range
blank
=
0C to
70C
(Commercial)
Package
PT
=
TQFP (Thin Quad Flatpack)
Pattern
QTP, SQTP, Code or Special Requirements L16 = 3V, 16 MHz
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices).
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 37
PIC16LC74B-16/PTL16
NOTES:
DS30026A-page 38
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
NOTES:
(c) 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 39
Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
* * *
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Japan
Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456
China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Chengdu
Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-6766200 Fax: 86-28-6766599
Taiwan
Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
China - Fuzhou
Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
EUROPE
Denmark
Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
China - Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Kokomo
2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086
New York
150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
Germany
Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Hong Kong
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Italy
Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
2002 Microchip Technology Inc.

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